The use of nanocrystals in non-volatile memories (NVMs) was primarily to have redundancy in each memory cell so that if there were a weak spot in a dielectric layer around the storage layer causing leakage of charge, then only a single nanocrystal in the storage layer would be adversely impacted and the remaining nanocrystals would still retain charge. There are typically difficulties with limited memory window, threshold voltage shift during program/erase cycling endurance, and read disturb of bits in a programmed state that are greater for nanocrystal NVM cells than for floating gate memory cells. The limited memory window arises from coulomb blockade effects that limit the charge storage capacity of the nanocrystals so that the total charge stored is less resulting in less threshold voltage differential between the logic high and logic low states. The program/erase cycling results in charge trapping, which can be cumulative, in the dielectric above the nanocrystals and thus reducing endurance. In the case of the floating gate, the charge is prevented from reaching the dielectric overlying the floating gate by the floating gate itself. Read disturb in bits that are in a programmed state arises due to the relatively higher field above the nanocrystals compared to the electric field above the floating gate in a floating gate device.
Thus, there is a need for NVM memory cells having nanocrystals overcoming or at least reducing these difficulties.